Chip design and layout
Scope
Design help before or after an MPW run: analog and mixed-signal blocks, RF and sensor front-ends, small RTL-to-GDS tasks, layout clean-up, DRC/LVS and tapeout checks. Start with goals, block type, node and timing; design files are shared only after an NDA.
Can help with
Design support
Analog, mixed-signal, RF and sensor blocks, quoted as a defined scope.
Tapeout readiness
PDK/NDA, DRC/LVS, package, test and schedule gaps found before the MPW run.
NDA first
Design detail is exchanged only after the NDA and the scope are agreed.
Required input
Support needed
Target node
Timing
Project outline
Deliverables
Scope and quote
List of gaps before tapeout
Proposed next step
Not accepted
Schematics, RTL, netlists, GDS/OASIS, PDK files or source code before an NDA
Export and compliance
Export-controlled or restricted technology needs clearance before work starts.
FAQ
What is Chip design and layout?
Design help before or after an MPW run: analog and mixed-signal blocks, RF and sensor front-ends, small RTL-to-GDS tasks, layout clean-up, DRC/LVS and tapeout checks. Start with goals, block type, node and timing; design files are shared only after an NDA.
What should I send first?
Support needed, Target node, Timing, Project outline
Can I upload confidential design files here?
Please do not send schematics, RTL, netlists, GDS/OASIS, PDK files or source code before an NDA.
Which export and compliance rules apply?
Export-controlled or restricted technology needs clearance before work starts.