Analog & power management
In stable mass production. Fit depends on voltage devices and reliability needs.
HHGRACE MPW SHUTTLE · 90 / 55 / 40 NM
Need a few chips? Get them from an HHGrace MPW shuttle
Send two details. MST replies by email with the process that fits, the next shuttle window and a written quote.
90 / 55 / 40 nmBare die or packaged samplesNo account neededSlot and price in writing
MPW COPILOT · AI
Check your process options and what still needs confirmation
Describe your chip. Compare published planning routes, find open reference windows and prepare questions for an engineering review.
- Intake completeness
- Planning candidates
- Shuttle windows for your target quarter
- A printable project brief to share
- No design files needed
TWO DETAILS
Send your MPW requirement
A work email and a short description are enough to start.
Do not send GDS/OASIS, RTL, netlists, source code or PDK files here.
AFTER YOU SEND
What happens next
- 1You send two details
- 2MST replies with a written quote and the shuttle window
- 3You accept the quote and pay
- 4MST starts your tape-out
Nothing is charged on this page. Price and shuttle window are set in the written quote.
Back to the formHUA HONG PROCESS FAMILIES
Which process family is closest to your chip?
From Hua Hong Semiconductor's 2025 annual report. The fit for your design is confirmed in the quote.
MCU & embedded memory
55 nm eFlash is in volume production; custom 40 nm eFlash entered pre-production in 2025.
Low-power logic & RF
40 nm ULP is in mass production for IoT and wearables; 55/40 nm specialty and RF CMOS are in stable production.
Same node, different process
Device options, memory macros and package/test decide the fit, not the node label alone.
THREE QUESTIONS
Three answers decide the process
What does the chip do?
Power/analog, embedded memory and logic use different processes.
How far is the design?
Concept, schematic, layout or tape-out-ready GDSII.
What should come back?
Bare die, packaged samples or tested parts.
Shuttle windows 2026Months and deadlines by node.Open schedule
HHGrace MPW SHUTTLE
HHGrace MPW shuttle windows 2026
Planned months per node.
| Node | Process family | Typical use | Months |
|---|---|---|---|
| 90nm | Low-power BCD | Mature-node BCD route for mixed-voltage and embedded-control requirements. | JanPastJunPastOctPlanned |
| 90nm | Embedded eFlash | Low-power embedded-memory route for control and specialty applications. | FebPastJulPastNovPlanned |
| 55nm | High-speed SiGe BiCMOS | Specialty mixed-signal route for high-speed and RF-oriented requirements. | JunPast |
| 55nm | Low-power BCD | Power-management and mixed-voltage route for qualified requirements. | AprPastNovPlanned |
| 55nm | Logic / embedded eFlash | Logic and embedded-memory planning route for qualified projects. | MarPastJunPastSepPastDecPlanned |
| 40nm | Logic / embedded eFlash | Low-power logic and embedded-memory planning route for qualified projects. | JanPastMayPastSepPast |
FAQ
Before you send
How do I start an HHGrace MPW project with MST?
Send the two-field form on this page. MST replies by email with the process that fits, the shuttle window and a written quote.
Which HHGrace processes can I use?
Hua Hong's 2025 annual report lists embedded and standalone non-volatile memory, power discrete, analog and power management, and logic and RF. Which one fits your design is confirmed in the quote.
Does any 90, 55 or 40 nm design fit a shuttle?
Not automatically. PDK access, slot and capacity depend on the design and are confirmed in the quote.
What should I send first?
Chip function, target node if known, design stage, timing, rough die area, and whether you need bare die, packaging or test. Do not send GDS, RTL, netlists or PDK files.
SOUTH KOREA · ENGLISH
MPW guide for South Korea teams
Process fit, PDK/NDA, GDSII readiness and package/test for fabless, startup and research teams in South Korea.
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