Analog & power management
The public report describes 90nm BCD as being in stable mass production and continuing to iterate. Fit still depends on voltage devices, BCD options and application reliability.
HHGRACE CUSTOMER ROUTE · HUMAN-REVIEWED
Need a few chips? Start an HHGrace-route MPW inquiry
Enter two details on this page. MST performs initial HHGrace-route triage, then follows up for the process, timing and package/test details needed for review.
90 / 55 / 40nmEstablished customer routeNo sign-inHuman-confirmed slot
TWO DETAILS · HUMAN-REVIEWED
Ask MST to review an HHGrace-route MPW inquiry
Share a work email and a short, non-confidential requirement. MST uses an established HHGrace customer route for initial routing, then follows up for the details needed before any process, timing, packaging or test path can be confirmed.
Do not submit GDS/OASIS, RTL, netlists, source code, PDK files or other confidential design IP through this public form.
PUBLIC HUA HONG PROCESS SIGNALS
Which publicly reported process family resembles your chip?
These are group-level routing clues from Hua Hong Semiconductor’s public 2025 reporting. They do not establish that any process is available through an HHGrace MPW route, or prove PDK, slot, capacity, data-acceptance or tapeout eligibility.
MCU & embedded memory
The report states that 55nm eFlash reached large-scale mass production, while customized 40nm eFlash products entered pre-production in 2025. Macro, PDK and qualification details remain case-specific.
Low-power logic & RF signals
The report separately covers 40nm ultra-low-power, 55/40nm specialty processes and RFCMOS; it does not explicitly map RFCMOS to both 55nm and 40nm. Initial routing considers power, frequency, device models and integration boundaries.
Same node does not mean same process fit
Chip function, device options, memory macros, design readiness, PDK/NDA, data acceptance, slot, package and test matter more than the “90/55/40nm” label alone.
Factual source: Hua Hong Semiconductor 2025 Annual Report (HKEX)
FIT BEFORE SCHEDULE
Three questions decide the route
What does the chip do?
Power / analog, embedded memory or logic changes the process route.
How ready is the design?
A concept, schematic, layout or clean GDSII each needs a different next step.
What must come back?
Bare die, package, electrical test and sample handling are separate decisions.
HUMAN COORDINATION
From two fields to an actionable path
- 1Enter a work email and non-confidential requirement
- 2MST screens process fit
- 3People confirm slot and terms
- 4Align package and test
Public schedules are screening references. Slot, price, PDK/NDA, data acceptance and tapeout eligibility are confirmed case by case.
Enter the requirementNeed the 2026 reference windows?The detailed schedule stays out of the way until you need it.Open schedule
2026 HHGrace MPW indicative windows
HHGrace 2026 MPW indicative planning windows
The nodes, public process families and indicative months support initial project planning only. Availability, schedule, PDK/NDA path, pricing, package/test scope and acceptance require fab confirmation after screening.
| Node | Public Process Family | Planning Scope | Indicative Months |
|---|---|---|---|
| 90nm | Low-power BCD | Mature-node BCD route for mixed-voltage and embedded-control requirements. | Jan · Jun · Oct |
| 90nm | Embedded eFlash | Low-power embedded-memory route for control and specialty applications. | Feb · Jul · Nov |
| 55nm | High-speed SiGe BiCMOS | Specialty mixed-signal route for high-speed and RF-oriented requirements. | Jun |
| 55nm | Low-power BCD | Power-management and mixed-voltage route for qualified requirements. | Apr · Nov |
| 55nm | Logic / embedded eFlash | Logic and embedded-memory planning route for qualified projects. | Mar · Jun · Sep · Dec |
| 40nm | Logic / embedded eFlash | Low-power logic and embedded-memory planning route for qualified projects. | Jan · May · Sep |
This page is not a booking calendar. Detailed submission dates and the current window are provided after project screening and remain subject to fab confirmation.
MPW INQUIRY FAQ
What should you know before sending an inquiry?
How can an overseas team start an HHGrace-route MPW inquiry through MST?
MST receives an initial non-confidential inquiry through an established HHGrace customer route and coordinates human follow-up. The public form is only an initial routing step; foundry acceptance, exact platform, PDK and NDA access, slot, capacity, data rules and commercial terms remain case-specific.
What specialty-process evidence is shown on this page?
Hua Hong Semiconductor publicly reports group-level process signals across embedded and standalone non-volatile memory, power discrete, analog and power management, and logic and RF. That reporting does not establish that a process is available through an HHGrace MPW route.
Can any 90nm, 55nm or 40nm design use an HHGrace MPW shuttle?
No. A node name or group annual report does not prove HHGrace MPW availability, design fit, PDK access, slot, capacity, data acceptance or tapeout eligibility. All require case-by-case confirmation.
What should an overseas fabless team send for an HHGrace MPW fit check?
Start with a non-confidential description of the chip function, target node if known, design stage, target timing, estimated die area and whether bare die, packaging or test is needed. Do not upload GDS, RTL, netlists or PDK files through the public form.
SOUTH KOREA BUYER PATH · ENGLISH
Make the prototype outcome reviewable before discussing a shuttle
A focused decision page for South Korea fabless, startup and research teams covering process fit, PDK/NDA, GDSII/DRC/LVS readiness, package/test and RFQ boundaries.
AFTER THE FIT CHECK
Enter only the workstream you need
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