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Incorpore una necesidad MPW de nodos maduros o procesos especializados antes de compartir IP de diseño. MST revisa nodo, familia de proceso, área de die, ruta PDK/NDA, encapsulado/prueba, ventana de calendario, país y uso final. La entrada pública no acepta GDS, OASIS, netlists, RTL, código fuente, archivos PDK ni IP propietaria.

Scope the post-wafer work that turns prototype silicon into usable samples: wafer dicing, bare-die handling, QFN/BGA/WLCSP or ceramic package assumptions, open-cavity needs, socket/load-board expectations, wafer probe, packaged test, sample quantity, shipment, and acceptance criteria. MST does not guarantee package availability, yield, schedule, or final pricing before partner review; we organize a qualified, case-by-case RFQ path after the high-level brief.

For teams that need help before or after MPW scoping: analog/mixed-signal blocks, RF or sensor front-ends, small RTL-to-GDS tasks, layout cleanup, DRC/LVS readiness, PDK/NDA handoff planning, and tapeout-readiness review. Intake is outline-first: share project goals, block type, node target, schedule and engagement scope only. Confidential schematics, source code, netlists, GDS, and PDK-bound material are handled only after the proper NDA path.