Chip design and layout RFQ
Alcance
For teams that need help before or after MPW scoping: analog/mixed-signal blocks, RF or sensor front-ends, small RTL-to-GDS tasks, layout cleanup, DRC/LVS readiness, PDK/NDA handoff planning, and tapeout-readiness review. Intake is outline-first: share project goals, block type, node target, schedule and engagement scope only. Confidential schematics, source code, netlists, GDS, and PDK-bound material are handled only after the proper NDA path.
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Design-scope screen
Classify what can be quoted as design support, layout support, review, or partner introduction.
Tapeout-readiness path
Identify likely gaps before MPW: PDK/NDA, DRC/LVS, package/test, schedule and ownership.
NDA-first engagement
Confidential design detail is exchanged only after the proper NDA and engagement scope.
Datos requeridos
Requested support
Target node / process range
Target timeline
Project outline
Entregables
Scope classification
Readiness-gap list
Next-step engagement path
No aceptado
Confidential schematics, RTL, netlists, GDS/OASIS, PDK files or proprietary source code at intake
Control de revisión
This is an outline-first RFQ. Do not submit confidential design IP at intake. Export-controlled or restricted technical content is held for manual review.
FAQ
What is Chip design and layout RFQ?
Outline-first RFQ for analog, mixed-signal, RF, sensor, layout, DRC/LVS and tapeout-readiness support before mature-node MPW.
What information should be submitted at intake?
Requested support, Target node / process range, Target timeline, Project outline
Can confidential design files be uploaded through public intake?
Public intake is non-confidential. Do not submit GDS, netlists, RTL, schematics, PDK files or proprietary design IP before the correct NDA and partner confirmation path.
Does MST review compliance or risk before routing this RFQ?
This is an outline-first RFQ. Do not submit confidential design IP at intake. Export-controlled or restricted technical content is held for manual review.